The present invention relates to random access memory for data storage. More specifically, the present invention relates to a magnetic random access memory device including an array of memory cells and circuitry for sensing resistance states of the memory cells.
Magnetic Random Access Memory ("MRAM") is a non-volatile memory that is being considered for long-term data storage. Performing read and write operations in MRAM devices would be orders of magnitude faster than performing read and write operations in conventional long-term storage devices such as hard drives. In addition, the MRAM devices would be more compact and would consume less power than hard drives and other conventional long-term storage devices.
A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
A memory cell stores a bit of information as an orientation of a magnetization. The magnetization of each memory cell assumes one of two stable orientations, or states, at any given time. These two stable orientations, parallel and anti-parallel, may represent logic values of `0` and `1.`
The magnetization orientation affects the resistance of a memory cell. For instance, resistance of a memory cell is a first value R if the magnetization orientation is parallel, and the resistance of the memory cell is a second value R+.DELTA.R if the magnetization orientation is anti-parallel. The magnetization orientation of a selected memory cell and, therefore, the logic state of the memory cell may be read by sensing the resistance state of the memory cell.
The resistance state of a selected memory cell may be read by applying a sense voltage to a word line crossing the selected memory cell and sensing a current on a bit line crossing the selected memory cell. The sense current (Is) is the ratio of the sense voltage (Vs) and the resistance of the selected memory cell (R or R+.DELTA.R). Thus, the sense current should be about equal to either Is.sub.0 =Vs/R or Is.sub.1 =Vs/(R+.DELTA.R). The sense current may be converted to a voltage. The resistance state of the selected memory cell may be determined by comparing the data voltage to a reference voltage (Vref). For example, the logic value stored in the selected memory cell is a logic `0` if the data voltage is greater than the reference voltage (that is, Vdata&gt;Vref), and the logic value is a logic `1` if the data voltage is less than the reference voltage (that is, Vdata&lt;Vref).
Generating reference signals for a large cross point resistive MRAM array is a complicated task. There is a loading effect of unselected memory cells. There are also "sneak paths" in the resistive array. Further, if manufacturing tolerances are not controlled adequately, there will be significant variations in memory cell resistances across the array. Consequently, a reference signal that is used by one group of memory cell might not be usable by another group of memory cells.
Generating the reference signals becomes increasingly complicated as device geometry is reduced. As the geometry is reduced, it becomes increasingly difficult to control manufacturing tolerances. Yet it is a goal of device manufacturers to decrease device geometry. Moreover, resistance variations can result from temperature gradients across the array, surrounding electro-magnetic noise, and physical effects such as aging.
There is a need to establish reliable reference signals for the memory cells of an MRAM array.